CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test

CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test

Introduction and Motivation -- SRAM Circuit Design and Operation -- SRAM Cell Stability: Definition, Modeling and Testing -- Traditional SRAM Fault Models and Test Practices -- Techniques for Detection of SRAM Cells with Stability Faults -- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Te...

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Bibliographic Details
Main Authors: Pavlov, Andrei, Sachdev, Manoj.
Format: Book
Language:English
Published: Springer 2017
Subjects:
Metal oxide semiconductors, Complementary
Design.
Random access memory.
Nanoelectronics.
621.38152
Online Access:http://repository.vnu.edu.vn/handle/VNU_123/27331
http://dx.doi.org/10.1007/978-1-4020-8363-1
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Institution: Vietnam National University, Hanoi
Language: English
Description
Summary:Introduction and Motivation -- SRAM Circuit Design and Operation -- SRAM Cell Stability: Definition, Modeling and Testing -- Traditional SRAM Fault Models and Test Practices -- Techniques for Detection of SRAM Cells with Stability Faults -- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques.

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