CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test

CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test

Introduction and Motivation -- SRAM Circuit Design and Operation -- SRAM Cell Stability: Definition, Modeling and Testing -- Traditional SRAM Fault Models and Test Practices -- Techniques for Detection of SRAM Cells with Stability Faults -- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Te...

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Main Authors: Pavlov, Andrei, Sachdev, Manoj.
Format: Book
Language:English
Published: Springer 2017
Subjects:
Metal oxide semiconductors, Complementary
Design.
Random access memory.
Nanoelectronics.
621.38152
Online Access:http://repository.vnu.edu.vn/handle/VNU_123/27331
http://dx.doi.org/10.1007/978-1-4020-8363-1
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Institution: Vietnam National University, Hanoi
Language: English
id oai:112.137.131.14:VNU_123-27331
record_format dspace
spelling oai:112.137.131.14:VNU_123-273312020-05-13T01:42:09Z CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test Pavlov, Andrei Sachdev, Manoj. Metal oxide semiconductors, Complementary Design. Random access memory. Nanoelectronics. 621.38152 Introduction and Motivation -- SRAM Circuit Design and Operation -- SRAM Cell Stability: Definition, Modeling and Testing -- Traditional SRAM Fault Models and Test Practices -- Techniques for Detection of SRAM Cells with Stability Faults -- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques. 2017-04-13T02:16:14Z 2017-04-13T02:16:14Z 2008 Book 9781402083624 9781402083631 http://repository.vnu.edu.vn/handle/VNU_123/27331 http://dx.doi.org/10.1007/978-1-4020-8363-1 en ©2008 Springer Science + Business Media B.V. 203 p. application/pdf Springer
institution Vietnam National University, Hanoi
building VNU Library & Information Center
country Vietnam
collection VNU Digital Repository
language English
topic Metal oxide semiconductors, Complementary
Design.
Random access memory.
Nanoelectronics.
621.38152
spellingShingle Metal oxide semiconductors, Complementary
Design.
Random access memory.
Nanoelectronics.
621.38152
Pavlov, Andrei
Sachdev, Manoj.
CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test
description Introduction and Motivation -- SRAM Circuit Design and Operation -- SRAM Cell Stability: Definition, Modeling and Testing -- Traditional SRAM Fault Models and Test Practices -- Techniques for Detection of SRAM Cells with Stability Faults -- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques.
format Book
author Pavlov, Andrei
Sachdev, Manoj.
author_facet Pavlov, Andrei
Sachdev, Manoj.
author_sort Pavlov, Andrei
title CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test
title_short CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test
title_full CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test
title_fullStr CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test
title_full_unstemmed CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test
title_sort cmos sram circuit design and parametric test in nano-scaled technologies : process-aware sram design and test
publisher Springer
publishDate 2017
url http://repository.vnu.edu.vn/handle/VNU_123/27331
http://dx.doi.org/10.1007/978-1-4020-8363-1
_version_ 1680963707213971456

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