A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4
Reconfigurable computing has been a computing method that further develops the processing speed of the software. It drastically increases the computing speed depending on the implementation and the hardware specifications. It requires manipulation of the hardware configurations in reconfigurable dev...
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| Main Authors: | , |
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| Format: | text |
| Language: | English |
| Published: |
Animo Repository
2011
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| Subjects: | |
| Online Access: | https://animorepository.dlsu.edu.ph/etd_bachelors/11314 |
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| Institution: | De La Salle University |
| Language: | English |
| Summary: | Reconfigurable computing has been a computing method that further develops the processing speed of the software. It drastically increases the computing speed depending on the implementation and the hardware specifications. It requires manipulation of the hardware configurations in reconfigurable devices in which Field Programmable Logic Array (FPGA) is one of the several devices that are capable of doing reconfiguration. With reconfiguration, the functionality of the logic gates in the programmable devices can be customized to further improve the computation speed.
The implementation of a reconfigurable Arithmetic Logic Unit (RALU) can be done in microprocessors. However, the real application of the implemented RALU can best be seen and use through interfacing in Input/output (I/O) devices such as keyboard, Video Graphics Array (VGA) monitor. With such implementation and interface, it can serve as a standalone computer.
This research aims to integrate the implemented RALU of Cardenas, et al. and the I/O interface by designing an I/O interface by designing an I/O module that can use the RALU and be utilized to the users application. |
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