A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4

Reconfigurable computing has been a computing method that further develops the processing speed of the software. It drastically increases the computing speed depending on the implementation and the hardware specifications. It requires manipulation of the hardware configurations in reconfigurable dev...

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Main Authors: Bravo, Christian Benedict, Ignacio, Marianne
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Language:English
Published: Animo Repository 2011
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Online Access:https://animorepository.dlsu.edu.ph/etd_bachelors/11314
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Institution: De La Salle University
Language: English
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spelling oai:animorepository.dlsu.edu.ph:etd_bachelors-119592021-10-04T02:48:25Z A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4 Bravo, Christian Benedict Ignacio, Marianne Reconfigurable computing has been a computing method that further develops the processing speed of the software. It drastically increases the computing speed depending on the implementation and the hardware specifications. It requires manipulation of the hardware configurations in reconfigurable devices in which Field Programmable Logic Array (FPGA) is one of the several devices that are capable of doing reconfiguration. With reconfiguration, the functionality of the logic gates in the programmable devices can be customized to further improve the computation speed. The implementation of a reconfigurable Arithmetic Logic Unit (RALU) can be done in microprocessors. However, the real application of the implemented RALU can best be seen and use through interfacing in Input/output (I/O) devices such as keyboard, Video Graphics Array (VGA) monitor. With such implementation and interface, it can serve as a standalone computer. This research aims to integrate the implemented RALU of Cardenas, et al. and the I/O interface by designing an I/O interface by designing an I/O module that can use the RALU and be utilized to the users application. 2011-01-01T08:00:00Z text https://animorepository.dlsu.edu.ph/etd_bachelors/11314 Bachelor's Theses English Animo Repository Adaptive computing systems Field programmable gate arrays Electrical and Electronics Engineering
institution De La Salle University
building De La Salle University Library
continent Asia
country Philippines
Philippines
content_provider De La Salle University Library
collection DLSU Institutional Repository
language English
topic Adaptive computing systems
Field programmable gate arrays
Electrical and Electronics
Engineering
spellingShingle Adaptive computing systems
Field programmable gate arrays
Electrical and Electronics
Engineering
Bravo, Christian Benedict
Ignacio, Marianne
A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4
description Reconfigurable computing has been a computing method that further develops the processing speed of the software. It drastically increases the computing speed depending on the implementation and the hardware specifications. It requires manipulation of the hardware configurations in reconfigurable devices in which Field Programmable Logic Array (FPGA) is one of the several devices that are capable of doing reconfiguration. With reconfiguration, the functionality of the logic gates in the programmable devices can be customized to further improve the computation speed. The implementation of a reconfigurable Arithmetic Logic Unit (RALU) can be done in microprocessors. However, the real application of the implemented RALU can best be seen and use through interfacing in Input/output (I/O) devices such as keyboard, Video Graphics Array (VGA) monitor. With such implementation and interface, it can serve as a standalone computer. This research aims to integrate the implemented RALU of Cardenas, et al. and the I/O interface by designing an I/O interface by designing an I/O module that can use the RALU and be utilized to the users application.
format text
author Bravo, Christian Benedict
Ignacio, Marianne
author_facet Bravo, Christian Benedict
Ignacio, Marianne
author_sort Bravo, Christian Benedict
title A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4
title_short A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4
title_full A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4
title_fullStr A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4
title_full_unstemmed A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4
title_sort vhdl implementation of an enhanced reconfigurable arithmetic logic unit implemented in virtex 4
publisher Animo Repository
publishDate 2011
url https://animorepository.dlsu.edu.ph/etd_bachelors/11314
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