Full-custom design and characterization of a phase locked loop - DLS565 using 0.5um CMOS technology
The DLS565 is a Phase-locked loop (PLL) Integrated Circuit (IC) design project simulated on all process corner libraries (TT, FF, SS, FS, SF) using 0.5um CMOS technology. The final IC design layout of the PLL without bonding pads covers approximately 0.46mm × 0.5mm. The parameters of the DLS565 were...
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Main Authors: | , , , , |
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Format: | text |
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Animo Repository
2014
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Online Access: | https://animorepository.dlsu.edu.ph/faculty_research/329 https://animorepository.dlsu.edu.ph/context/faculty_research/article/1328/type/native/viewcontent |
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Institution: | De La Salle University |