Full-custom design and characterization of a phase locked loop - DLS565 using 0.5um CMOS technology

• Main Authors: Atendido, Kenneth Martin C., Co, Justin Daniel C., Navarro, Jose Gianmarco B., Garcia, Pamela Candice H., Abad, Alexander C.
• Format: text
• Published: Animo Repository 2014
• Subjects: Phase-locked loops; Phase detectors; Voltage-controlled oscillators; Metal oxide semiconductors, Complementary; Electrical and Electronics
• Online Access: https://animorepository.dlsu.edu.ph/faculty_research/329; https://animorepository.dlsu.edu.ph/context/faculty_research/article/1328/type/native/viewcontent
• Institution: De La Salle University

The DLS565 is a Phase-locked loop (PLL) Integrated Circuit (IC) design project simulated on all process corner libraries (TT, FF, SS, FS, SF) using 0.5um CMOS technology. The final IC design layout of the PLL without bonding pads covers approximately 0.46mm × 0.5mm. The parameters of the DLS565 were...