Flexible architecture for analogue delay line
The latest circuit provides a flexible architecture for analogue delay lines (ADL), which is useful for both low and high frequencies. The latest design of ADLs, based on the circuit, consists of four basic blocks, such as an analogue-to-digital converter (ADC), a static memory device (SRAM), a digi...
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| Main Authors: | , |
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| Format: | text |
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Animo Repository
2008
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| Online Access: | https://animorepository.dlsu.edu.ph/faculty_research/3590 |
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| Institution: | De La Salle University |
| Summary: | The latest circuit provides a flexible architecture for analogue delay lines (ADL), which is useful for both low and high frequencies. The latest design of ADLs, based on the circuit, consists of four basic blocks, such as an analogue-to-digital converter (ADC), a static memory device (SRAM), a digital-to-analogue converter (DAC), and an address counter (AC). The AC provides an extra output bit that is used to toggle the switches. Samples from the ADC are stored in the memory block, which consists of a pair of 15-bit CMOS static RAMs. The addresses of the SRAMs are generated by a cascade of four 4-bit synchronous binary counters. Stored samples are read by a current-mode R-2R ladder DAC that reconstructs a time-delayed version of the analogue input. |
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