Flexible architecture for analogue delay line

The latest circuit provides a flexible architecture for analogue delay lines (ADL), which is useful for both low and high frequencies. The latest design of ADLs, based on the circuit, consists of four basic blocks, such as an analogue-to-digital converter (ADC), a static memory device (SRAM), a digi...

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Main Authors:	Edang, E., Dela Cruz, Hadrian D.
Format:	text
Published:	Animo Repository 2008
Subjects:	Delay lines Static random access memory Electrical and Electronics
Online Access:	https://animorepository.dlsu.edu.ph/faculty_research/3590
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Institution:	De La Salle University

id	oai:animorepository.dlsu.edu.ph:faculty_research-4592
record_format	eprints
spelling	oai:animorepository.dlsu.edu.ph:faculty_research-45922021-09-17T05:45:52Z Flexible architecture for analogue delay line Edang, E. Dela Cruz, Hadrian D. The latest circuit provides a flexible architecture for analogue delay lines (ADL), which is useful for both low and high frequencies. The latest design of ADLs, based on the circuit, consists of four basic blocks, such as an analogue-to-digital converter (ADC), a static memory device (SRAM), a digital-to-analogue converter (DAC), and an address counter (AC). The AC provides an extra output bit that is used to toggle the switches. Samples from the ADC are stored in the memory block, which consists of a pair of 15-bit CMOS static RAMs. The addresses of the SRAMs are generated by a cascade of four 4-bit synchronous binary counters. Stored samples are read by a current-mode R-2R ladder DAC that reconstructs a time-delayed version of the analogue input. 2008-11-01T07:00:00Z text https://animorepository.dlsu.edu.ph/faculty_research/3590 Faculty Research Work Animo Repository Delay lines Static random access memory Electrical and Electronics
institution	De La Salle University
building	De La Salle University Library
continent	Asia
country	Philippines Philippines
content_provider	De La Salle University Library
collection	DLSU Institutional Repository
topic	Delay lines Static random access memory Electrical and Electronics
spellingShingle	Delay lines Static random access memory Electrical and Electronics Edang, E. Dela Cruz, Hadrian D. Flexible architecture for analogue delay line
description	The latest circuit provides a flexible architecture for analogue delay lines (ADL), which is useful for both low and high frequencies. The latest design of ADLs, based on the circuit, consists of four basic blocks, such as an analogue-to-digital converter (ADC), a static memory device (SRAM), a digital-to-analogue converter (DAC), and an address counter (AC). The AC provides an extra output bit that is used to toggle the switches. Samples from the ADC are stored in the memory block, which consists of a pair of 15-bit CMOS static RAMs. The addresses of the SRAMs are generated by a cascade of four 4-bit synchronous binary counters. Stored samples are read by a current-mode R-2R ladder DAC that reconstructs a time-delayed version of the analogue input.
format	text
author	Edang, E. Dela Cruz, Hadrian D.
author_facet	Edang, E. Dela Cruz, Hadrian D.
author_sort	Edang, E.
title	Flexible architecture for analogue delay line
title_short	Flexible architecture for analogue delay line
title_full	Flexible architecture for analogue delay line
title_fullStr	Flexible architecture for analogue delay line
title_full_unstemmed	Flexible architecture for analogue delay line
title_sort	flexible architecture for analogue delay line
publisher	Animo Repository
publishDate	2008
url	https://animorepository.dlsu.edu.ph/faculty_research/3590
_version_	1767195936738508800

Flexible architecture for analogue delay line

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