Simulation and FPGA-based implementation of iterative parallel schedulers for optical interconnection networks

• Main Authors: Cerutti, Isabella, Corvera, Jan Alain, Dumlao, Samuel Matthew, Reyes, Rosula SJ, Castoldi, Piero, Andriolli, Nicola
• Format: text
• Published: Archīum Ateneo 2017
• Subjects: Hardware programming; Interconnection network; Optical interconnects; Packet switching; Scheduling; Electrical and Computer Engineering
• Online Access: https://archium.ateneo.edu/ecce-faculty-pubs/4; https://ieeexplore.ieee.org/document/7901448
• Institution: Ateneo De Manila University

High-performance interconnection networks are required for inter-board, intra-board, and on-chip data communication. With the growth of data communication, the requirements for high bandwidth density, high scalability, low latency, and low power consumption are becoming more stringent, making optical solutions appealing. Such requirements should be achieved not only by the hardware architecture but also by the electronic scheduler that is in charge of deciding the packet transmissions and controlling the optical devices. In particular, low-latency schedulers are of paramount importance-especially for optical interconnection networks whose switching capabilities may be constrained by the optical domain. This paper focuses on the hardware implementation and optimization of a scheduler suitable for optical interconnection networks. Parallel, iterative scheduling algorithms are considered for high computational efficiency. More specifically, an iterative parallel implementation of the longestqueue- first algorithm (ipLQF) is proposed and compared to the well-known iSLIP algorithm. Hardware optimization is carried out to improve their implementation efficiency. Although ipLQF achieves better network performance in terms of packet latency, the hardware implementation indicates that iSLIP stands for execution time and resource utilization in commercial field programmable gate array boards.