Hardware Comparison of Schedulers for Modular Optical Interconnection Networks

We present the first FPGA implementation of the Two-Step Scheduler framework for modular optical interconnection networks. The longest-queue-first scheduling algorithm guarantees the lowest latency, while the iSLIP algorithm minimizes the hardware resources and scheduling duration.

Saved in:
書目詳細資料
Main Authors: Borromeo, J C, Cerutti, Isabella, Castoldi, Piero, Reyes, Rosula SJ, Andriolli, Nicola
格式: text
出版: Archīum Ateneo 2019
主題:
在線閱讀:https://archium.ateneo.edu/ecce-faculty-pubs/32
https://ieeexplore.ieee.org/abstract/document/8818053
標簽: 添加標簽
沒有標簽, 成為第一個標記此記錄!
機構: Ateneo De Manila University