Hardware Comparison of Schedulers for Modular Optical Interconnection Networks

We present the first FPGA implementation of the Two-Step Scheduler framework for modular optical interconnection networks. The longest-queue-first scheduling algorithm guarantees the lowest latency, while the iSLIP algorithm minimizes the hardware resources and scheduling duration.

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Main Authors: Borromeo, J C, Cerutti, Isabella, Castoldi, Piero, Reyes, Rosula SJ, Andriolli, Nicola
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Published: Archīum Ateneo 2019
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Online Access:https://archium.ateneo.edu/ecce-faculty-pubs/32
https://ieeexplore.ieee.org/abstract/document/8818053
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Institution: Ateneo De Manila University
id ph-ateneo-arc.ecce-faculty-pubs-1031
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spelling ph-ateneo-arc.ecce-faculty-pubs-10312020-06-09T06:21:58Z Hardware Comparison of Schedulers for Modular Optical Interconnection Networks Borromeo, J C Cerutti, Isabella Castoldi, Piero Reyes, Rosula SJ Andriolli, Nicola We present the first FPGA implementation of the Two-Step Scheduler framework for modular optical interconnection networks. The longest-queue-first scheduling algorithm guarantees the lowest latency, while the iSLIP algorithm minimizes the hardware resources and scheduling duration. 2019-01-01T08:00:00Z text https://archium.ateneo.edu/ecce-faculty-pubs/32 https://ieeexplore.ieee.org/abstract/document/8818053 Electronics, Computer, and Communications Engineering Faculty Publications Archīum Ateneo Optical switching technologies for high-performance computing and data centers Modelling design implementation Impairment mitigation algorithms for advanced switching functionality Electrical and Computer Engineering
institution Ateneo De Manila University
building Ateneo De Manila University Library
continent Asia
country Philippines
Philippines
content_provider Ateneo De Manila University Library
collection archium.Ateneo Institutional Repository
topic Optical switching technologies for high-performance computing and data centers
Modelling
design
implementation
Impairment mitigation
algorithms for advanced switching functionality
Electrical and Computer Engineering
spellingShingle Optical switching technologies for high-performance computing and data centers
Modelling
design
implementation
Impairment mitigation
algorithms for advanced switching functionality
Electrical and Computer Engineering
Borromeo, J C
Cerutti, Isabella
Castoldi, Piero
Reyes, Rosula SJ
Andriolli, Nicola
Hardware Comparison of Schedulers for Modular Optical Interconnection Networks
description We present the first FPGA implementation of the Two-Step Scheduler framework for modular optical interconnection networks. The longest-queue-first scheduling algorithm guarantees the lowest latency, while the iSLIP algorithm minimizes the hardware resources and scheduling duration.
format text
author Borromeo, J C
Cerutti, Isabella
Castoldi, Piero
Reyes, Rosula SJ
Andriolli, Nicola
author_facet Borromeo, J C
Cerutti, Isabella
Castoldi, Piero
Reyes, Rosula SJ
Andriolli, Nicola
author_sort Borromeo, J C
title Hardware Comparison of Schedulers for Modular Optical Interconnection Networks
title_short Hardware Comparison of Schedulers for Modular Optical Interconnection Networks
title_full Hardware Comparison of Schedulers for Modular Optical Interconnection Networks
title_fullStr Hardware Comparison of Schedulers for Modular Optical Interconnection Networks
title_full_unstemmed Hardware Comparison of Schedulers for Modular Optical Interconnection Networks
title_sort hardware comparison of schedulers for modular optical interconnection networks
publisher Archīum Ateneo
publishDate 2019
url https://archium.ateneo.edu/ecce-faculty-pubs/32
https://ieeexplore.ieee.org/abstract/document/8818053
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