Design of non-destructive single-sawtooth pulse based readout for STT-RAM by NVM-SPICE
Spin-transfer torque random access memory (STTRAM) is one promising candidate for future non-volatile memory based computing, because of its fast access time, high integration density and non-volatility. One major challenge of STT-RAM is to design robust readout circuit in the presence of large...
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| Main Authors: | , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/100923 http://hdl.handle.net/10220/18298 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Spin-transfer torque random access memory (STTRAM)
is one promising candidate for future non-volatile memory
based computing, because of its fast access time, high integration
density and non-volatility. One major challenge of STT-RAM
is to design robust readout circuit in the presence of large
MTJ resistance variations. The lack of SPICE-like platform
hinders the design validation for hybrid STT-MTJ and CMOS
memory structure and readout circuits. In this paper, we have
introduced the recently developed NVM-SPICE for the design
of STT-RAM with large memory array and also non-destructive
single-sawtooth pulse based STT-RAM readout. Compared to
the simulation by equivalent circuit, the NVM-SPICE shows
117x faster simulation time for large-array STT-RAM. Moreover,
validated by the NVM-SPICE, the proposed single-sawtooth pulse
based readout shows 2x faster read latency with 8x larger sensing
margin than the existing readout schemes. |
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