Design of non-destructive single-sawtooth pulse based readout for STT-RAM by NVM-SPICE

• Main Authors: Wang, Yuhao, Shang, Yang, Yu, Hao
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/100923; http://hdl.handle.net/10220/18298
• 機構: Nanyang Technological University

Spin-transfer torque random access memory (STTRAM) is one promising candidate for future non-volatile memory based computing, because of its fast access time, high integration density and non-volatility. One major challenge of STT-RAM is to design robust readout circuit in the presence of large MTJ resistance variations. The lack of SPICE-like platform hinders the design validation for hybrid STT-MTJ and CMOS memory structure and readout circuits. In this paper, we have introduced the recently developed NVM-SPICE for the design of STT-RAM with large memory array and also non-destructive single-sawtooth pulse based STT-RAM readout. Compared to the simulation by equivalent circuit, the NVM-SPICE shows 117x faster simulation time for large-array STT-RAM. Moreover, validated by the NVM-SPICE, the proposed single-sawtooth pulse based readout shows 2x faster read latency with 8x larger sensing margin than the existing readout schemes.