A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os
One memory-logic-integration design platform is developed in this paper with thermal reliability analysis provided for 2.5D through-silicon-interposer (TSI) and 3D through-silicon-via (TSV) based integrations. Temperature-dependent delay and power models have been developed at microarchitecture leve...
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| Main Authors: | , , , , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2015
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/105539 http://hdl.handle.net/10220/25512 http://dx.doi.org/10.7873/DATE.2014.190 |
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| Institution: | Nanyang Technological University |
| Language: | English |