A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

• Main Authors: Kim, Tony Tae-Hyoung, Lee, Zhao Chuan, Do, Anh Tuan
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: Bitline Sensing; DRNTU::Engineering::Electrical and electronic engineering; Static Random Access Memory
• Online Access: https://hdl.handle.net/10356/105826; http://hdl.handle.net/10220/48769; http://dx.doi.org/10.1016/j.sse.2017.10.002
• Institution: Nanyang Technological University

Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V.