An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability

• Main Authors: Chen, Junchao, Chong, Kwen-Siong, Gwee, Bah Hwee, Chang, Joseph Sylvester
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/106455; http://hdl.handle.net/10220/17694; http://dx.doi.org/10.1109/ISCAS.2012.6271625
• Institution: Nanyang Technological University

We propose a dynamic voltage scalable SRAM capable of efficient bit-interleaving in column to tolerate multiple-bits soft error when integrated with error correction codes (ECC). First, a 10T SRAM bitcell is proposed. It activates only intended bitcells so that stability problem of half-selected bit...