An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability
We propose a dynamic voltage scalable SRAM capable of efficient bit-interleaving in column to tolerate multiple-bits soft error when integrated with error correction codes (ECC). First, a 10T SRAM bitcell is proposed. It activates only intended bitcells so that stability problem of half-selected bit...
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Main Authors: | , , , |
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格式: | Conference or Workshop Item |
語言: | English |
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2013
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在線閱讀: | https://hdl.handle.net/10356/106455 http://hdl.handle.net/10220/17694 http://dx.doi.org/10.1109/ISCAS.2012.6271625 |
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機構: | Nanyang Technological University |
語言: | English |