3D simulation-based research on the effect of interconnect structures on circuit reliability

• Main Authors: He, Feifei, Tan, Cher Ming
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/107007; http://hdl.handle.net/10220/25292; http://www.worldacademicunion.com/journal/1746-7233WJMS/wjmsvol08no04paper03.pdf
• Institution: Nanyang Technological University

Electromigration (EM) of the interconnects is a key factor in determining the reliability of an integrated circuit, especially for the present-day IC with shrinking interconnect dimension. The simulation of the EM reliability of the interconnects is usually performed using the line-via structure at the EM test temperature (e.g. 300 oC).However, such simulation using the line-via structure may not give the same void nucleation location as in the real circuit structure, especially at the circuit operation temperature (e.g. 90C). This change in failure site can cause mis-interpretation of the EM weak spot location when the line-via structure is used for data extrapolation in predicting the EM reliability of the entire circuit. This drives the need for the reliability simulation using a complete 3D circuit model. In this paper, we build several 3D models of a simple circuit with different interconnect structures and examine the effect of the layout structural changes, such as the via and contact positions and their numbers, the inter-transistor distance, the metal structure and layer number, on the circuit EM reliability. 3D circuit model. In this paper, we build several 3D models of a simple circuit with different interconnect structures and examine the effect of the layout structural changes, such as the via and contact positions and their numbers, the inter-transistor distance, the metal structure and layer number, on the circuit EM reliability. A 585.40% improvement in the EM lifetime can be obtained by using Metal 1 as the output line instead of the metal/via stacks, while a 136.97% reduction in the EM lifetime is observed when the number of contacts of the transistor reduces from 6 to 3.The simulation results are consistent with the experimental results in the literature and thus validate the capability of performing the EM lifetime comparison of different interconnect structures using the 3D circuit model.