A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory

• Main Authors: Chun, Ki Chul, Zhao, Hui, Harms, Jonathan D., Kim, Tony Tae-Hyoung, Wang, Jian-Ping, Kim, Chris H.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/107155; http://hdl.handle.net/10220/18037; http://dx.doi.org/10.1109/JSSC.2012.2224256
• Institution: Nanyang Technological University

This paper explores the scalability of in-plane and perpendicular MTJ based STT-MRAMs from 65 nm to 8 nm while taking into consideration realistic variability effects. We focus on the read and write performances of a STT-MRAM based cache rather than the obvious advantages such as the denser bit-cell...