Path oriented boolean test generation for single stuck-at fault in combinational circuits

• Main Author: Zhang, Xudong
• Other Authors: Chin, Edward Hsi Ling
• Format: Theses and Dissertations
• Language: English
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits; DRNTU::Engineering::Computer science and engineering::Theory of computation::Analysis of algorithms and problem complexity
• Online Access: http://hdl.handle.net/10356/13164
• Institution: Nanyang Technological University

To produce reliable electronic systems, defect-free components must be available. Automatic test pattern generation systems distinguish defective components from defect-free components by generating input sets that cause the outputs of a component under test to be different if the component is defective than if it is defect-free. As the logic circuits under test get larger, generating tests is becoming harder. Test generation has been proved to be a NP-complete problem.