Low power CMOS memory circuit design

• Main Author: Foo, Chee Heng
• Other Authors: Lau K T
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/138635
• Institution: Nanyang Technological University

Two novel SRAM is proposed and simulated with TSMC 40nm technology. Both novel 10T SRAM is designed to be used under low power supply, with features such as low power consumption and high reading static noise margin. Both proposed SRAM can operate under supply voltage as low as 0.31V. Under this supply voltage, it has read static noise margin of 107 mV, which is more than three times better compared to the conventional 6T SRAM. The first novel 10T SRAM is designed using multi-threshold voltage technique, where the four reading transistors have higher threshold than the other transistors. The second novel 10T SRAM use transistors with same threshold voltage. The first novel 10T SRAM has improvement in read delay of 184.1 ns and overall power consumption compared to 9T SRAM in previous research which also uses multi-threshold voltage technique. The second novel 10T SRAM has significant improvement in read delay, which is only 16.34 ns, with trade-off of less than 10% increase in power consumption.