Low power CMOS memory circuit design

Low power CMOS memory circuit design

Two novel SRAM is proposed and simulated with TSMC 40nm technology. Both novel 10T SRAM is designed to be used under low power supply, with features such as low power consumption and high reading static noise margin. Both proposed SRAM can operate under supply voltage as low as 0.31V. Under this sup...

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書目詳細資料
主要作者:	Foo, Chee Heng
其他作者:	Lau K T
格式:	Final Year Project
語言:	English
出版:	Nanyang Technological University 2020
主題:	Engineering::Electrical and electronic engineering::Integrated circuits
在線閱讀:	https://hdl.handle.net/10356/138635
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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