Hardware optimized and error reduced approximate adder

• Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas Leslie
• Other Authors: School of Computer Science and Engineering
• Format: Article
• Language: English
• Published: 2020
• Subjects: Engineering::Computer science and engineering; Approximate Computing; Approximate Adder
• Online Access: https://hdl.handle.net/10356/142855
• Institution: Nanyang Technological University

This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)-and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 20...