14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques

• Main Authors: Wu, Tony F., Le, Binh Q., Radway, Robert, Bartolo, Andrew, Hwang, William, Jeong, Seungbin, Li, Haitong, Tandon, Pulkit, Vianello, Elisa, Vivet, Pascal, Nowak, Etienne, Wootters, Mary K., Wong, Philip H.-S., Mohamed M. Sabry Aly, Beigne, Edith, Mitra, Subhasish
• Other Authors: School of Computer Science and Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2020
• Subjects: Engineering::Computer science and engineering; System-On-Chip; Nonvolatile Memory
• Online Access: https://hdl.handle.net/10356/143358
• Institution: Nanyang Technological University

Non-volatility is emerging as an essential on-chip memory characteristic across a wide range of application domains, from edge nodes for the Internet of Things (IoT) to large computing clusters. On-chip non-volatile memory (NVM) is critical for low-energy operation, real-time responses, privacy and security, operation in unpredictable environments, and fault-tolerance [1]. Existing on-chip NVMs (e.g., Flash, FRAM, EEPROM) suffer from high read/write energy/latency, density, and integration challenges [1]. For example, an ideal IoT edge system would employ fine-grained temporal power gating (i.e., shutdown) between active modes. However, existing on-chip Flash can have long latencies (> 23 ms latency for erase followed by write), while inter-sample arrival times can be short (e.g., 2ms in [2]).