Uniform delayering of copper metallization

Uniform delayering of copper metallization

Integrated circuit chips of newer technology usually have a larger die size and an increase number of metallization. Hence, pure usage of polishing to remove the layers would induce severe edge rounding. An alternative method is proposed to decrease the polishing time for copper metallization remova...

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Main Authors: Siah, Yu Wen, Hong, Y. J., Liu, Q., Kor, Katherine Hwee Boon, Gan, C. L.
Other Authors: School of Materials Science and Engineering
Format: Conference or Workshop Item
Language:English
Published: 2020
Subjects:
Engineering::Materials
Delayering
Sample Preparation
Online Access:https://hdl.handle.net/10356/143510
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1435102020-09-26T22:15:12Z Uniform delayering of copper metallization Siah, Yu Wen Hong, Y. J. Liu, Q. Kor, Katherine Hwee Boon Gan, C. L. School of Materials Science and Engineering 2013 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Temasek Laboratories Engineering::Materials Delayering Sample Preparation Integrated circuit chips of newer technology usually have a larger die size and an increase number of metallization. Hence, pure usage of polishing to remove the layers would induce severe edge rounding. An alternative method is proposed to decrease the polishing time for copper metallization removal while reducing edge rounding on the sample during sample preparation that will preserve the integrity of the layers for further failure analysis. Accepted version 2020-09-07T04:29:00Z 2020-09-07T04:29:00Z 2013 Conference Paper Siah, Y. W., Hong, Y. J., Liu, Q., Kor, K. H. B., & Gan, C. L. (2013). Uniform delayering of copper metallization. 2013 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 166-169. doi:10.1109/IPFA.2013.6599147 9781479912414 https://hdl.handle.net/10356/143510 10.1109/IPFA.2013.6599147 2-s2.0-84885673786 166 169 en © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, in any current or future media, including reprinting/republishing this material for adverstising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at:https://doi.org/10.1109/IPFA.2013.6599147 application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic Engineering::Materials
Delayering
Sample Preparation
spellingShingle Engineering::Materials
Delayering
Sample Preparation
Siah, Yu Wen
Hong, Y. J.
Liu, Q.
Kor, Katherine Hwee Boon
Gan, C. L.
Uniform delayering of copper metallization
description Integrated circuit chips of newer technology usually have a larger die size and an increase number of metallization. Hence, pure usage of polishing to remove the layers would induce severe edge rounding. An alternative method is proposed to decrease the polishing time for copper metallization removal while reducing edge rounding on the sample during sample preparation that will preserve the integrity of the layers for further failure analysis.
author2 School of Materials Science and Engineering
author_facet School of Materials Science and Engineering
Siah, Yu Wen
Hong, Y. J.
Liu, Q.
Kor, Katherine Hwee Boon
Gan, C. L.
format Conference or Workshop Item
author Siah, Yu Wen
Hong, Y. J.
Liu, Q.
Kor, Katherine Hwee Boon
Gan, C. L.
author_sort Siah, Yu Wen
title Uniform delayering of copper metallization
title_short Uniform delayering of copper metallization
title_full Uniform delayering of copper metallization
title_fullStr Uniform delayering of copper metallization
title_full_unstemmed Uniform delayering of copper metallization
title_sort uniform delayering of copper metallization
publishDate 2020
url https://hdl.handle.net/10356/143510
_version_ 1681056631979245568

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