A highly efficient power model for Correlation Power Analysis (CPA) of pipelined Advanced Encryption Standard (AES)

• Main Authors: Ng, Jun-Sheng, Chen, Juncheng, Kyaw, Nay Aung, Lwin, Ne Kyaw Zwa, Ho, Weng-Geng, Chong, Kwen-Siong, Gwee, Bah-Hwee
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; Pipelined Advanced Encryption Standard (AES); Hardware Security
• Online Access: https://hdl.handle.net/10356/146374
• Institution: Nanyang Technological University

We evaluate the vulnerability of a pipelined Advanced Encryption Standard (AES) against Correlation Power Analysis (CPA) Side-Channel Attack (SCA). We identify that the registers in pipelined AES are most vulnerable against CPA SCA and propose a new power model targeting the switching activities of the registers. The proposed power model is constructed based on the Hamming Distance (HD) between the intermediate values stored in the registers in two consecutive clock cycles. Then, we analyze the vulnerability of pipelined AES under two scenarios. First, during regular pipeline operation where the device is performing AES pipeline operation. Second, in non-pipeline operation where we assume the adversaries can insert delay to the input of the device to increase the signal to noise ratio of the physical leakage information. The simulation results show that under regular pipelined operation, our proposed power model can reveal all the 16 key bytes in less than 4,900 traces, resulting in 4.7× more effective than the conventional power models. Under non-pipelined operation, our proposed power model requires only 590 traces to reveal all the 16 key bytes, which is 5.9× more effective than other power models.