A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS

• Main Authors: Palaniappan, Arjun Ramaswami, Siek, Liter
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; Time-To-Digital Converter (TDC); Vernier Delay Line
• Online Access: https://hdl.handle.net/10356/152105
• Institution: Nanyang Technological University

A new vernier delay line time-to-digital converter (TDC) capable of achieving an ultra-fine resolution at an ultra-low supply voltage is designed in 180 nm / 1.8 V CMOS process. The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built using capacitive boosting delay buffers capable of amplifying the input time signals higher than the supply and below the ground for driving the subsequent buffers with improved strength even at an ultra-low operating supply voltage. The proposed 6-bit CB-VDL TDC achieves an ultra-fine resolution of 1.74 ps while operating at an ultra-low supply of 0.6 V and consumes a power of 217.43 μW at a sampling frequency of 50 MHz, thus making it highly suitable for applications such as low power all-digital phase locked loops, time-of-flight measurement systems and time-mode analog-to-digital converters. The TDC core occupies an area of 1.225 mm 2 including the on-chip calibration unit in 180 nm CMOS.