A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS
A new vernier delay line time-to-digital converter (TDC) capable of achieving an ultra-fine resolution at an ultra-low supply voltage is designed in 180 nm / 1.8 V CMOS process. The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built...
Saved in:
Main Authors: | Palaniappan, Arjun Ramaswami, Siek, Liter |
---|---|
Other Authors: | School of Electrical and Electronic Engineering |
Format: | Conference or Workshop Item |
Language: | English |
Published: |
2021
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/152105 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC
by: Kong, Junjie, et al.
Published: (2021) -
A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS
by: Teh, Jian Sen, et al.
Published: (2021) -
Efficiency optimization of permanent magnet vernier for direct-drive application
by: Yeo, Jun Rong
Published: (2024) -
A 0.0186 mm2, 0.65 V supply, 9.53 ps RMS jitter all-digital PLL for medical implants
by: Palaniappan, Arjun Ramaswami, et al.
Published: (2021) -
3-5 GHz 4-channel UWB beamforming transmitter with 1° scanning resolution through calibrated vernier delay line in 0.13-μm CMOS
by: Wang, L., et al.
Published: (2014)