A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS

• Main Authors: Palaniappan, Arjun Ramaswami, Siek, Liter
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2021
• 主題: Engineering::Electrical and electronic engineering; Time-To-Digital Converter (TDC); Vernier Delay Line
• 在線閱讀: https://hdl.handle.net/10356/152105
• 機構: Nanyang Technological University

A new vernier delay line time-to-digital converter (TDC) capable of achieving an ultra-fine resolution at an ultra-low supply voltage is designed in 180 nm / 1.8 V CMOS process. The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built...