Low power-delay-product (PDP) CMOS multiplier design

• Main Author: Leng, Xiaoxiang
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2021
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/154152
• Institution: Nanyang Technological University

Multiplier is an important part of the microprocessor, which determines the performance of the system, and plays a pivotal role in image processing, speech recognition and other fields. A 16-bit low power-delay-product (PDP) multiplier is proposed in this dissertation and several techniques are combined to improve its performance. In algorithm level, modified Booth algorithm is applied to reduce the number of partial products from 16 to 9. Furthermore, sign extension method for Booth algorithm is also used for reducing the bits of each partial product. In architecture level, according to the result of modified Booth algorithm, a special Dadda tree is designed for partial product accumulation. Since there are 9 partial products in total, 3-2 compressors are used to compress them. And a ripple carry adder is designed for final addition. After using Verilog to descibe the circuit, the synthesis and simulation of the circuit is done with the help of simulation tools including Design Compiler and Verilog Compiled Simulator. The result shows that the Power-Delay-Product of the proposed design is lower than that of the array multiplier and Booth multiplier, 63% and 21% respectively.