Design of low-power high speed error-tolerant adder and its application in digital signal processing

• 主要作者: Zhang, Weijia
• 其他作者: Yeo Kiat Seng
• 格式: Theses and Dissertations
• 語言: English
• 出版: 2009
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing
• 在線閱讀: https://hdl.handle.net/10356/15559

As technology advances, errors/defects in integrated circuits become unavoidable. At the same time, the pursuit of low-power and high-speed circuits is always restricted by the conventional circuit design technology. In this context, several new technologies that regard the accuracy of circuit as a new design parameter other than the conventional design metrics have been proposed. These technologies trade the accuracy of circuit for the improvements in power consumption and/or speed performance. Stimulated by those emerging technologies, a novel and innovative type of adder, the Error-Tolerant Adder (ETA), is proposed. The detailed theoretical studies and circuit designs of two different realizations of this new type of adder are presented in this thesis. By incorporating special addition algorithms and circuit structures, and sacrificing certain degree of accuracy, the proposed ETA is able to achieve significant improvements in power consumption and speed performance as compared to the conventional adders. To illustrate the practicality of the proposed ETA in real applications, the Fast Fourier Transform (FFT) function, which is a basic and important function in Digital Signal Processing (DSP), is taken as the platform to employ the proposed designs. This ETA-based FFT function is put in the context of digital image processing to demonstrate its functionality. Simulation results show that with a well-designed ETA, the ETA-based FFT function can be used in digital image processing to generate acceptable results.