UVM testbench development for Quad-SPI controller

With the increase in the scale and complexity of Integrated Circuits, the difficulty and workload of verification increase accordingly. Traditional verification methodologies take much time to develop testbenches and testcases. So, improving the efficiency and quality of verification has become a ho...

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Main Author: Yu, Zehui
Other Authors: Chang Chip Hong
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2022
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Online Access:https://hdl.handle.net/10356/155989
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1559892023-07-04T17:43:53Z UVM testbench development for Quad-SPI controller Yu, Zehui Chang Chip Hong School of Electrical and Electronic Engineering Silicon Laboratories International Pte. Ltd. Technical University of Munich Joash Tan ECHChang@ntu.edu.sg Engineering::Electrical and electronic engineering::Integrated circuits With the increase in the scale and complexity of Integrated Circuits, the difficulty and workload of verification increase accordingly. Traditional verification methodologies take much time to develop testbenches and testcases. So, improving the efficiency and quality of verification has become a hot topic in the digital integrated circuit verification field. This dissertation uses Universal Verification Methodology with reusable architecture with multiple objects, components, and mechanisms to improve the verification efficiency. The history of verification methodologies as well as the architecture and components of Universal Verification Methodology are reviewed before the verification project. Serial Peripheral Interface is a synchronous serial data transmission protocol, which is applied in more and more integrated circuits because of its simple pin connection. Quad-SPI controller communicates with external Flashes Single/Dual/Quad SPI protocol and handles different functional modes and Flash instructions. The dissertation analyzed and extracted functional points of the Quad-SPI controller. Then a UVM testbench is developed with basic UVM components and Verification Components. Some testcases for main functional modes are also developed based on the UVM testbench. Finally, code and functional coverages are collected with current testcases. Master of Science (Integrated Circuit Design) 2022-03-27T13:45:21Z 2022-03-27T13:45:21Z 2022 Thesis-Master by Coursework Yu, Z. (2022). UVM testbench development for Quad-SPI controller. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/155989 https://hdl.handle.net/10356/155989 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle Engineering::Electrical and electronic engineering::Integrated circuits
Yu, Zehui
UVM testbench development for Quad-SPI controller
description With the increase in the scale and complexity of Integrated Circuits, the difficulty and workload of verification increase accordingly. Traditional verification methodologies take much time to develop testbenches and testcases. So, improving the efficiency and quality of verification has become a hot topic in the digital integrated circuit verification field. This dissertation uses Universal Verification Methodology with reusable architecture with multiple objects, components, and mechanisms to improve the verification efficiency. The history of verification methodologies as well as the architecture and components of Universal Verification Methodology are reviewed before the verification project. Serial Peripheral Interface is a synchronous serial data transmission protocol, which is applied in more and more integrated circuits because of its simple pin connection. Quad-SPI controller communicates with external Flashes Single/Dual/Quad SPI protocol and handles different functional modes and Flash instructions. The dissertation analyzed and extracted functional points of the Quad-SPI controller. Then a UVM testbench is developed with basic UVM components and Verification Components. Some testcases for main functional modes are also developed based on the UVM testbench. Finally, code and functional coverages are collected with current testcases.
author2 Chang Chip Hong
author_facet Chang Chip Hong
Yu, Zehui
format Thesis-Master by Coursework
author Yu, Zehui
author_sort Yu, Zehui
title UVM testbench development for Quad-SPI controller
title_short UVM testbench development for Quad-SPI controller
title_full UVM testbench development for Quad-SPI controller
title_fullStr UVM testbench development for Quad-SPI controller
title_full_unstemmed UVM testbench development for Quad-SPI controller
title_sort uvm testbench development for quad-spi controller
publisher Nanyang Technological University
publishDate 2022
url https://hdl.handle.net/10356/155989
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