Design of a low noise low voltage preamplifier

A low noise low voltage preamplifier is designed in this project. Using a 0.18 μm CMOS technology, a two-stage CMOS folded cascode operational amplifier with class AB output buffer is designed utilizing Cadence Custom IC Design Tool. The preamplifier is biased by a constant-transconductance bias cir...

全面介紹

Saved in:
書目詳細資料
主要作者: Yeoh, Kuan Seong.
其他作者: Siek Liter
格式: Final Year Project
語言:English
出版: 2009
主題:
在線閱讀:http://hdl.handle.net/10356/15705
標簽: 添加標簽
沒有標簽, 成為第一個標記此記錄!