Deep learning-based image analysis framework for hardware assurance of digital integrated circuits

• Main Authors: Lin, Tong, Shi, Yiqiong, Shu, Na, Cheng, Deruo, Hong, Xuenong, Song, Jingsi, Gwee, Bah Hwee
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2022
• Subjects: Engineering::Electrical and electronic engineering; Hardware Assurance; Digital ICs
• Online Access: https://hdl.handle.net/10356/159572
• Institution: Nanyang Technological University

We propose a complete Artificial Intelligence (AI)/Deep Learning (DL)-based image analysis framework for hardware assurance of digital integrated circuits (ICs). Our aim is to examine and verify various hardware information by analyzing the Scanning Electron Microscope (SEM) images of an IC. In our proposed framework, we make use of DL-based methods at all essential steps of the analysis. To the best of our knowledge, this is the first such framework that makes heavy use of DL-based methods at all essential analysis steps. For image analysis tasks such as stitching misalignment detection and stacking movement regression that were previously performed mainly manually, we propose novel DL-based method and novel DL model architecture to automate these tasks. One of the salient features of our proposed framework is the heavy use of automated and semi-automated methods in preparing training data and the use of synthetic data to train a DL model. We also propose to train a preliminary DL model for training data preparation in scenarios where the noise level of the image set is high. Further, to maximally encourage model re-use, we propose various DL models that can operate on feature images thus applicable to new image sets without model re-training. By applying our proposed framework to analyzing a set of SEM images of a large digital IC, we prove its efficacy. Our DL-based methods are fast, accurate, robust against noise, and can automate tasks that were previously performed mainly manually. Overall, we show that, by applying our proposed various DL-based methods, we can largely increase the level of automation in hardware assurance of digital ICs and improve its accuracy.