Design of a CMOS relaxation oscillator with reduced circuit sensitivity

• Main Author: Liao, Yizhuo
• Other Authors: Chan Pak Kwong
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/163611
• Institution: Nanyang Technological University

A fully-integrated CMOS relaxation oscillator which is realized in 40nm CMOS technology is presented. The oscillator includes a stable 2-Transistor based voltage reference without operational amplifier, a simple current reference employing the temperature-compensated composite resistor and the approximated Complementary-to-Absolute-Temperature (CTAT) delay based comparators compensate the approximated Proportional-to-Absolute-Temperature (PTAT) delay arising from the leakage currents in switches. This relaxation oscillator is designed to output a square wave with frequency of 64kHz in duty cycle of 50% at 1.1V supply. The simulation results have demonstrated that the circuit can generate a square wave with stable frequency against temperature and supply variation whilst consuming low current consumption. For temperature range from -20°C to 80°C at 1.1V supply, the oscillator’ output frequency has achieved temperature coefficient (T.C.) of 12.4 ppm/°C in typical corner in one sample simulation. For 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corner and room temperature, the simulated line sensitivity is 0.045%/V over the supply from 1.1V to 1.6V and the dynamic current consumption is 552nA. A better figure-of-merit (FOM), which equals to 0.129%, is displayed when compared to the representative prior-art works.