The effective verification method for analog and digital PLL

• المؤلف الرئيسي: Tang, Jinfei
• مؤلفون آخرون: Gwee Bah Hwee
• التنسيق: Thesis-Master by Coursework
• اللغة: English
• منشور في: Nanyang Technological University 2023
• الموضوعات: Engineering::Electrical and electronic engineering
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/166544
• المؤسسة: Nanyang Technological University

With the increasing complexity and integration of SOCs, more and more analog blocks are added to the digital blocks, and the application of digital-analog mixed-signal systems becomes more common. The simulation accuracy and performance parameters of the analog part will be lost. This dissertation combines the established mixed-signal modelling methods to analyse and model the PLL modules to achieve a compromise between simulation speed and accuracy to meet the requirements and needs of mixed-signal system verification. This dissertation explains the basic structure and principles of phase-locked loops, builds a top-level test platform for phase-locked loops, tests each module one by one, analyses the function and output of each module of the PLL, and rewrites the module in the form of Verilog AMS to imitate the function of the module as realistically as possible. Then replace the top-level testbed module in the schematic with the Verilog AMS model and observe whether the output waveform and frequency of each module match with the theoretical circuit, to verify the function of the AMS module. The final output of AMS model simulation is very close to that of schematic and greatly improves the simulation speed.