Dual-gate all-electrical valleytronic transistors
The development of integrated circuits (ICs) based on a complementary metal−oxide−semiconductor through transistor scaling has reached the technology bottleneck; thus, alternative approaches from new physical mechanisms are highly demanded. Valleytronics in two-dimensional (2D) material systems h...
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| Main Authors: | , , , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2023
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/166606 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | The development of integrated circuits (ICs) based on a complementary
metal−oxide−semiconductor through transistor scaling has reached the technology
bottleneck; thus, alternative approaches from new physical mechanisms are highly
demanded. Valleytronics in two-dimensional (2D) material systems has recently emerged
as a strong candidate, which utilizes the valley degree of freedom to process information for
electronic applications. However, for all-electrical valleytronic transistors, very low room-
temperature “valley on−off” ratios (around 10) have been reported so far, which seriously limits their practical applications. In this
work, we successfully illustrated both n- and p-type valleytronic transistor performances in monolayer MoS2 and WSe2 devices, with
measured “valley on−off” ratios improved up to 3 orders of magnitude greater compared to previous reports. Our work shows a
promising way for the electrically controllable manipulation of valley degree of freedom toward practical device applications. |
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