Dual-gate all-electrical valleytronic transistors

• Main Authors: Lai, Shen, Zhang, Zhaowei, Wang, Naizhou, Abdullah Rasmita, Deng, Ya, Liu, Zheng, Gao, Weibo
• Other Authors: School of Physical and Mathematical Sciences
• Format: Article
• Language: English
• Published: 2023
• Subjects: Science::Physics; All-Electrical; Valleytronic Transistor; “Valley on−off” Ratios; Valley Degree of Freedom
• Online Access: https://hdl.handle.net/10356/166606
• Institution: Nanyang Technological University

The development of integrated circuits (ICs) based on a complementary metal−oxide−semiconductor through transistor scaling has reached the technology bottleneck; thus, alternative approaches from new physical mechanisms are highly demanded. Valleytronics in two-dimensional (2D) material systems has recently emerged as a strong candidate, which utilizes the valley degree of freedom to process information for electronic applications. However, for all-electrical valleytronic transistors, very low room- temperature “valley on−off” ratios (around 10) have been reported so far, which seriously limits their practical applications. In this work, we successfully illustrated both n- and p-type valleytronic transistor performances in monolayer MoS2 and WSe2 devices, with measured “valley on−off” ratios improved up to 3 orders of magnitude greater compared to previous reports. Our work shows a promising way for the electrically controllable manipulation of valley degree of freedom toward practical device applications.