High speed multiplier IC design based on booth algorithm
It designed a high speed 32-bit signed multiplier based on Booth algorithm, 4-2 compressor using Wallace Tree structure and Carry-Look-Ahead adder. This design is 47. 03% faster than the original 32-bit signed shift multiplier, according to the length of critical path. The proposed design is also be...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
| Published: |
Nanyang Technological University
2023
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| Online Access: | https://hdl.handle.net/10356/166865 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | It designed a high speed 32-bit signed multiplier based on Booth algorithm, 4-2 compressor using Wallace Tree structure and Carry-Look-Ahead adder. This design is 47. 03% faster than the original 32-bit signed shift multiplier, according to the length of critical path. The proposed design is also better in power consumption, area and FPGA resources after synthesis process. It has a decrease of 28. 64%, 42. 01%, 47. 64% in power consumption, area and FPGA resources after synthesis process respectively. |
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