High speed multiplier IC design based on booth algorithm

• Main Author: Chang, Shuming
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/166865
• Institution: Nanyang Technological University

It designed a high speed 32-bit signed multiplier based on Booth algorithm, 4-2 compressor using Wallace Tree structure and Carry-Look-Ahead adder. This design is 47. 03% faster than the original 32-bit signed shift multiplier, according to the length of critical path. The proposed design is also be...