High speed multiplier IC design based on booth algorithm

It designed a high speed 32-bit signed multiplier based on Booth algorithm, 4-2 compressor using Wallace Tree structure and Carry-Look-Ahead adder. This design is 47. 03% faster than the original 32-bit signed shift multiplier, according to the length of critical path. The proposed design is also be...

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Main Author:	Chang, Shuming
Other Authors:	Gwee Bah Hwee
Format:	Thesis-Master by Coursework
Language:	English
Published:	Nanyang Technological University 2023
Subjects:	Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:	https://hdl.handle.net/10356/166865
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Institution:	Nanyang Technological University
Language:	English

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spelling	sg-ntu-dr.10356-1668652023-07-04T16:47:40Z High speed multiplier IC design based on booth algorithm Chang, Shuming Gwee Bah Hwee School of Electrical and Electronic Engineering ebhgwee@ntu.edu.sg Engineering::Electrical and electronic engineering::Electronic circuits It designed a high speed 32-bit signed multiplier based on Booth algorithm, 4-2 compressor using Wallace Tree structure and Carry-Look-Ahead adder. This design is 47. 03% faster than the original 32-bit signed shift multiplier, according to the length of critical path. The proposed design is also better in power consumption, area and FPGA resources after synthesis process. It has a decrease of 28. 64%, 42. 01%, 47. 64% in power consumption, area and FPGA resources after synthesis process respectively. Master of Science (Electronics) 2023-05-11T05:05:18Z 2023-05-11T05:05:18Z 2023 Thesis-Master by Coursework Chang, S. (2023). High speed multiplier IC design based on booth algorithm. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/166865 https://hdl.handle.net/10356/166865 en application/pdf Nanyang Technological University
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle	Engineering::Electrical and electronic engineering::Electronic circuits Chang, Shuming High speed multiplier IC design based on booth algorithm
description	It designed a high speed 32-bit signed multiplier based on Booth algorithm, 4-2 compressor using Wallace Tree structure and Carry-Look-Ahead adder. This design is 47. 03% faster than the original 32-bit signed shift multiplier, according to the length of critical path. The proposed design is also better in power consumption, area and FPGA resources after synthesis process. It has a decrease of 28. 64%, 42. 01%, 47. 64% in power consumption, area and FPGA resources after synthesis process respectively.
author2	Gwee Bah Hwee
author_facet	Gwee Bah Hwee Chang, Shuming
format	Thesis-Master by Coursework
author	Chang, Shuming
author_sort	Chang, Shuming
title	High speed multiplier IC design based on booth algorithm
title_short	High speed multiplier IC design based on booth algorithm
title_full	High speed multiplier IC design based on booth algorithm
title_fullStr	High speed multiplier IC design based on booth algorithm
title_full_unstemmed	High speed multiplier IC design based on booth algorithm
title_sort	high speed multiplier ic design based on booth algorithm
publisher	Nanyang Technological University
publishDate	2023
url	https://hdl.handle.net/10356/166865
_version_	1772826956596772864

High speed multiplier IC design based on booth algorithm

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