A single-channel voltage-scalable 8-GS/s 8-b > 37.5-dB SNDR time-domain ADC with asynchronous pipeline successive approximation in 28-nm CMOS

• Main Authors: Chen, Qian, Boon, Chirn Chye, Liu, Qing, Liang, Yuan
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2023
• Subjects: Engineering::Electrical and electronic engineering; Asynchronous Pipeline Successive Approximation; High Speed
• Online Access: https://hdl.handle.net/10356/167258
• Institution: Nanyang Technological University

This article presents a single-channel voltage-scalable 8-GS/s 8-b time-domain analog-to-digital-converter (TD-ADC). It breaks the speed limit of traditional TD-ADC by leveraging asynchronous pipeline successive approximation (APSA), which reduces the quantization period to approximate one-stage time-domain comparator decision time. A co-design methodology of voltage-to-time converter (VTC) and time-to-digital converter (TDC) is proposed to optimize the ADC linearity without increasing the complexity or power consumption, reducing the linearity request of VTC. In addition, concurrent charge redistribution and voltage pull-up is deployed in the VTC, supporting the rail-to-rail input and enabling voltage scalability. The TD-ADC is fabricated in 28-nm CMOS and occupies an active area of 0.011 mm 2 , demonstrating 39.2-dB signal-to-noise-distortion ratio (SNDR) and 56.1-dB spurious-free dynamic range (SFDR) at 0.9 V, 8-GS/s with 85.3-mW power dissipation and 37.6-dB SNDR and 56.3 dB SFDR at 0.7 V, 5.05 GS/s with 23.1-mW power dissipation, achieving 143.1-and 74.3-fJ/conv.-step Nyquist Walden figure of merit (FoM W ), respectively.