Fabrication and characterization of through silicon via interconnects for 3D IC packages

• Main Author: Huang, Weiqin.
• Other Authors: Miao Jianmin
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Manufacturing
• Online Access: http://hdl.handle.net/10356/16870
• Institution: Nanyang Technological University

The advancement in technology and higher standards of living has brought along an increasing demand for higher performance microelectronic devices. Through Wafer Interconnect (TWI) technology is responsible for fabricating the future three dimensional Integrated circuit packaging that offers higher speed and greater performance of the micromechanical systems. Since replacing aluminium as the key material for fabricating TWI, copper electroplating techniques has been the interest in the area of research in the fabrication process. The quest to fabricate interconnects with higher aspect ratios with the elimination of voids has been the driving force to further develop and improvise the existing electroplating techniques that can realize these possibilities. The conventional plating techniques adopted for fabrication is the reverse pulse plating techniques, which has proven itself in obtaining better plating results compared to continuous Direct Current (DC) and pulse current plating techniques. However, in recent years, in review to this particular electroplating processes, results has shown that Pulse reverse plating techniques incorporated with aspect ratio conditions has shown better reliability in obtaining void free copper interconnect. Through wafer etching adopting the Deep Reactive Ion Etching (DRIE) process has also been a great concern to obtaining higher aspect ratio through via, with improved surface roughness on the side walls, affecting the grain size of the copper deposits along the through via which determines its mechanical properties. The mechanical and electrical properties of the copper interconnect are an important integral in determining the performance of the system. Different electroplating parameters can yield different results on these properties. In this project we only focus on the fabrication processes and the mechanical characterization of the copper TWI. The electroplating technique we will be using for plating the through wafer is the pulse reverse plating. With different electroplating current densities and through via diameters, we have observed the corresponding difference in the hardness and modulus of the plated copper in the through via. The highlight of these results shows that higher current density has brought along a reduction in the average hardness and modulus value of the copper TWI with the same though via diameter. And also we have shown the location dependence characteristics of the hardness and modulus value as their nano-indentation positions varies along the copper TWI. An abrupt change in the increment of hardness value has been observed at positions along the sidewall of the copper interconnect, which suggested a change in the grain structure from the side wall with the central column of the copper TWI that has brought about the change. Further studies were carried out on observing the grain size of the copper deposits and results has shown that smaller grains are obtained at the side wall of the copper TWI during the electroplating process. These findings further supported the indentation results that smaller grains constitute to a higher hardness and modulus value. In addition, different via diameters of the copper TWI has also shown deviation in their hardness and modulus value as positions defer. However there is no observable trend to suggest the relationship of hardness and modulus value with via diameter generally.