A time-domain wavefront computing accelerator with a 32 × 32 reconfigurable PE array
This work presents a hardware accelerator realizing true time-domain wavefront computing in a massive parallel two-dimensional (2-D) processing element (PE) array. The proposed 2-D time-domain PE array is designed for multiple applications based on its scalable and reconfigurable architecture. The s...
Saved in:
Main Authors: | Yu, Chengshuo, Mu, Junjie, Su, Yuqi, Chai, Kevin Tshun Chuan, Kim, Tony Tae-Hyoung, Kim, Bongjin |
---|---|
Other Authors: | School of Electrical and Electronic Engineering |
Format: | Article |
Language: | English |
Published: |
2023
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/170677 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
A 65-nm 8T SRAM compute-in-memory macro with column ADCs for processing neural networks
by: Yu, Chengshuo, et al.
Published: (2022) -
A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems
by: Su, Yuqi, et al.
Published: (2022) -
Reconfigurable 2T2R ReRAM architecture for versatile data storage and computing in-memory
by: Chen, Yuzong, et al.
Published: (2022) -
A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation
by: Kim, Tony Tae-Hyoung, et al.
Published: (2019) -
A digital bit-reconfigurable versatile compute-in-memory macro for machine learning acceleration
by: Zhang, Xin, et al.
Published: (2023)