Simulation of post-breakdown transistor performance in ultrathin gate dielectrics-based nanoscale MOSFETs

• Main Author: Yaw, Meng Kwan.
• Other Authors: Pey Kin Leong
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
• Online Access: http://hdl.handle.net/10356/17188
• Institution: Nanyang Technological University

The purpose of this project is to simulate the post-breakdown transistor performance in ultrathin gate dielectric. The simulator used was TSUPREM-4 and MEDICI, which is widely used in the semiconductor industry for simulation and analyze semiconductor processing. The simulation was done on a 0.13μm metal-oxide-semiconductor field-effect transistor (MOSFET) which has silicon and silicon oxide defects introduced into the gate dielectric. Various different doping defects and silicon oxide defects are added into the simulation to test for the post-breakdown I-V characteristics of the transistor.