Advancing chip-level communication: a comparative analysis of conventional, smart, and ARSmart network-on-chip architectures

• Main Author: Peh, Elijah Kai En
• Other Authors: Weichen Liu
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering
• Online Access: https://hdl.handle.net/10356/175118
• Institution: Nanyang Technological University

This Final Year Project (FYP) report presents a comprehensive analysis of Software Defined on-Chip Networking within Network-on-Chip (NoC) architectures, specifically focusing on conventional NoC, SMART NoC, and ArSMART NoC designs. It investigates these architectures through simulations to assess their performance, particularly in terms of latency and power efficiency. The research is motivated by the advancements in multi-core processor technology, necessitating improved on-chip communication networks to handle the increased complexity and demands of modern computing systems efficiently. The study uses the Gem5 simulation environment to compare the traditional NoC, SMART NoC, and ArSMART NoC, focusing on metrics such as latency, power consumption, and overall efficiency in multi-core processors. The SMART NoC system, recognized for its efficient data traversal mechanism, is compared against traditional NoC as well as the ArSMART NoC, which builds upon the SMART system by offering enhanced routing flexibility validated through Gem5 simulations. The report details the methodology for the comparative analysis, system design and implementation, challenges faced during simulations, and experimental results. Experimental results show that SMART NoC significantly reduces latency and potentially enhances processor efficiency and energy savings compared to conventional NoC designs. However, due to simulation constraints, conclusive data for ArSMART NoC was not obtained, highlighting an area for future research. The report concludes with suggestions for future improvements in NoC designs, emphasizing the need for advanced routing solutions, power efficiency initiatives, scalability frameworks, fault tolerance mechanisms, and dynamic topology reconfiguration. It also outlines directions for future research, including empirical evaluation of ArSMART NoC, targeted energy efficiency research, workload-specific performance assessments, long-term system reliability studies, and cross-disciplinary NoC design exploration. This analysis contributes to the understanding of on-chip communication networks' efficiency and effectiveness, laying the groundwork for further exploration and development of sophisticated NoC systems to meet the demands of modern multi-core computing systems.