Design of a 800-MHZ PLL in 28NM CMOS technology

• 主要作者: Tao, Weiran
• 其他作者: Goh Wang Ling
• 格式: Thesis-Master by Coursework
• 語言: English
• 出版: Nanyang Technological University 2024
• 主題: Engineering; 28nm CMOS; Type–two charge pump PLL; Type–four PFD; Cascaded differential LC–VCO; Adjustable digital divider; Rail–to–rail output voltage; Low mismatch, spur and noise
• 在線閱讀: https://hdl.handle.net/10356/175977

This dissertation proposes a type–two analog PLL based on charge pump with division ratio of 20 and output frequency of up to 0.8GHz, which has been validated in 28nm CMOS technology system. The input signal is passed through a classic type–four phase and frequency detector, and then the current cha...