Quantum correction hardware accelerator design on FPGA

• Main Author: Soh, Siang Yang
• Other Authors: Goh Wang Ling
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Quantum error correction hardware accelerator; Verilog neural network
• Online Access: https://hdl.handle.net/10356/176232
• Institution: Nanyang Technological University

This project investigates alternative hardware solutions for quantum error correction, focusing on replacing the slow and computationally expensive MWPM error decoder with more efficient methods. Through thorough prototyping and evaluation, the Connected Neural Network (NN) approach emerged as the superior candidate over the Compressed Look-up Table (CLUT) method. The NN decoder demonstrates high performance with lower implementation memory requirements, especially for larger models, and seamless transition from software to hardware through quantization. The NN decoder hardware architecture comprises multiple modules, including neuron, layer, and model modules, which collectively enable efficient computation and interconnection. The final implementation effectively replicates software model performance with acceptable deviation due to activation approximation error. Notably, it exhibits efficient resource utilization on FPGA, particularly in fixed 8 model, indicating potential for minimizing power consumption. The estimated decoding time of 0.15 microseconds for NN decoder signifies a monumental improvement over MWPM algorithm, which required 0.15 seconds for similar decoding. This reduction underscores transformative potential of hardware-based solutions in quantum error correction, promising accelerated error correction processes in future quantum computing systems.