Quantum correction hardware accelerator design on FPGA

• Main Author: Soh, Siang Yang
• Other Authors: Goh Wang Ling
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Quantum error correction hardware accelerator; Verilog neural network
• Online Access: https://hdl.handle.net/10356/176232
• Institution: Nanyang Technological University

This project investigates alternative hardware solutions for quantum error correction, focusing on replacing the slow and computationally expensive MWPM error decoder with more efficient methods. Through thorough prototyping and evaluation, the Connected Neural Network (NN) approach emerged as the s...