Design and simulation of CMOS-based ternary logic arithmetic circuits using TSMC 40nm technology

• المؤلف الرئيسي: Vivekanantham, Rithikha
• مؤلفون آخرون: Tay Beng Kang
• التنسيق: Final Year Project
• اللغة: English
• منشور في: Nanyang Technological University 2024
• الموضوعات: Engineering
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/176639

In recent years, there has been growing interest in multi-valued logic (MVL) circuits, especially ternary logic circuits, due to their higher information density compared to binary logic systems. However, challenges persist regarding the fundamental construction of MVL circuit standard cells and the...