A versatile approach for adaptive grid mapping and grid flex-graph exploration with a field-programmable gate array-based robot using hardware schemes

• Main Authors: Basha, Mudasar, Siva Kumar, Munuswamy, Chinnaiah, Mangali Chinna, Lam, Siew-Kei, Srikanthan, Thambipillai, Divya Vani, Gaddam, Janardhan, Narambhatla, Dodde, Hari Krishna, Dubey, Sanjay
• Other Authors: College of Computing and Data Science
• Format: Article
• Language: English
• Published: 2024
• Subjects: Computer and Information Science; Single robot; Robotic exploration
• Online Access: https://hdl.handle.net/10356/178521
• Institution: Nanyang Technological University

Robotic exploration in dynamic and complex environments requires advanced adaptive mapping strategies to ensure accurate representation of the environments. This paper introduces an innovative grid flex-graph exploration (GFGE) algorithm designed for single-robot mapping. This hardware-scheme-based algorithm leverages a combination of quad-grid and graph structures to enhance the efficiency of both local and global mapping implemented on a field-programmable gate array (FPGA). This novel research work involved using sensor fusion to analyze a robot's behavior and flexibility in the presence of static and dynamic objects. A behavior-based grid construction algorithm was proposed for the construction of a quad-grid that represents the occupancy of frontier cells. The selection of the next exploration target in a graph-like structure was proposed using partial reconfiguration-based frontier-graph exploration approaches. The complete exploration method handles the data when updating the local map to optimize the redundant exploration of previously explored nodes. Together, the exploration handles the quadtree-like structure efficiently under dynamic and uncertain conditions with a parallel processing architecture. Integrating several algorithms into indoor robotics was a complex process, and a Xilinx-based partial reconfiguration approach was used to prevent computing difficulties when running many algorithms simultaneously. These algorithms were developed, simulated, and synthesized using the Verilog hardware description language on Zynq SoC. Experiments were carried out utilizing a robot based on a field-programmable gate array (FPGA), and the resource utilization and power consumption of the device were analyzed.